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rev 1.6 7/16/03 1 of 21 www.xicor.com dual two-wiper digitally-controlled (xdcp) potentiometer features dual two-wiper solid state potentiometer 256 resistor tap points?.4% resolution 2-wire serial interface for write, read, and transfer operations of the potentiometer up/down interface for individual potentiometer wipers wiper resistance, 40 ? typical non-volatile storage of wiper positions power on recall loads saved wiper position on power up. standby current < 20? max maximum wiper current: 3ma ? cc : 2.7v to 5.5v operation 2.8k ? , 10k ? , 50k ? , 100k ? version of total pot resistance endurance: 100,000 data changes per bit per register 100 yr. data retention 24-lead tssop description the X9455 integrates 2 digitally controlled potentiome- ters (xdcp), each one with dual wipers, on a mono- lithic cmos integrated circuit. the digitally controlled potentiometer is implemented using 255 resistive elements in a series array. between each element are tap points connected to wiper termi- nals through switches. the position of each wiper on the array is controlled by the user through the u/d or 2-wire bus interface. each potentiometer wiper has associated with it two volatile wiper counter register (wcr) and each wcr has associated with it four non- volatile data registers that can be directly written to and read by the user. the contents of the wcr con- trols the position of the wiper on the resistor array though the switches. the contents of the default data registers (dr0a0, dr0b0, dr1a0, dr1b0) are loaded into the wcr on power up. the dcp can be used as a four-terminal potentiometer in a wide variety of applications including the program- ming of bias voltages, window comparators, and three resistor programmable networks. functional diagram v cc v ss 2-wire r w0a a0 a1 sda scl cs u/d a2 ds0 ds1 wp wcr0a dr0a0 dr0a1 dr0a2 dr0a3 r h0 r l0 dcp0 wcr0b dr0b0 dr0b1 dr0b2 dr0b3 r w0b r w1a wcr1a dr1a0 dr1a1 dr1a2 dr1a3 r h1 r l1 dcp1 wcr1b dr1b1 dr1b2 dr1b3 r w1b powerup, interface control and status interface up/down interface dr1b0 X9455 new features dual wipers dual interface
2 of 21 rev 1.6 7/16/03 www.xicor.com X9455 pin configuration tssop rh1 nc rw1a 1 2 3 4 5 6 7 14 20 19 18 17 16 15 X9455 ds0 ds1 a0 rw0b u/ d nc scl rl1 vss nc rw0a cs rh0 rl0 rw1b nc vcc 8 9 10 13 wp a2 11 12 sda a1 24 23 22 21 ordering information ordering number rtotal package operating temperature range X9455yv24-2.7 2.8k ? 24-lead tssop 0? to 70? X9455yv24i-2.7 2.8k ? 24-lead tssop -40? to +85? X9455wv24-2.7 10k ? 24-lead tssop 0? to 70? X9455wv24i-2.7 10k ? 24-lead tssop -40? to +85? X9455uv24-2.7 50k ? 24-lead tssop 0? to 70? X9455uv24i-2.7 50k ? 24-lead tssop -40? to +85? X9455tv24-2.7 100k ? 24-lead tssop 0? to 70? X9455tv24i-2.7 100k ? 24-lead tssop -40? to +85?
3 of 21 rev 1.6 7/16/03 www.xicor.com X9455 pin assignments tssop pin symbol brief description 1 ds0 wiper selection input for up/down interface 2 a0 device address for 2-wire interface 3 rw0b second wiper terminal of dcp0 4 nc no connect 5 nc no connect 6u/d increment/decrement for up/down interface 7 vcc system supply voltage 8 rl0 low terminal of dcp0 9 rh0 high terminal of dcp0 10 rw0a first wiper terminal of the dcp0 11 a2 device address for 2-wire interface 12 wp hardware write protect (active low) 13 sda serial data input/output for 2-wire interface 14 a1 device address for 2-wire interface 15 nc no connect 16 nc no connect 17 rw1b second wiper terminal of dcp1 18 vss system ground 19 cs chip select for up/down interface 20 rw1a first wiper terminal of dcp1 21 rh1 high terminal of dcp1 22 rl1 low terminal of dcp1 23 scl serial clock for 2-wire interface 24 ds1 wiper selection input for up/down interface
X9455 4 of 21 rev 1.6 7/16/03 www.xicor.com absolute maximum ratings junction temperature under bias ......?5 c to +135 c storage temperature .........................?5 c to +150 c voltage at any digital interface pin with respect to v ss .................................. ?v to +7v v cc ............................................................ ?v to +7v voltage at any dcp pin with respect to v ss ..........................................-1v to v cc lead temperature (soldering, 10 seconds).........300 c i w (10 seconds) ................................................. ?ma comment stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; the functional operation of the device (at these or any other conditions above those listed in the operational sections of this speci?a- tion) is not implied. exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. recommended operating conditions temp min. max. commercial 0 c +70 c industrial ?0 c +85 c device supply voltage (v cc ) (4) limits X9455 2.7v to 5.5v analog characteristics (over recommended operating conditions unless otherwise stated.) symbol parameter limits test conditions min. typ. (4) max. unit r total end to end resistance 2.8, 10, 50, 100 k ? y, w, u, t versions respectively end to end resistance tolerance -20 +20 % power rating 50 mw 25?, each dcp r total matching dcp to dcp resistance matching 0.75 2.0 % i w (5) wiper current -3.0 +3.0 ma see test circuit r w wiper resistance 50 150 ? wiper current = v term voltage on any dcp pin vss vcc v noise (5) -120 dbv ref: 1khz resolution 0.4 % absolute linearity (1) ? +1 mi (3) v(r h0 )=v(r h1 )=v cc v(r l0 )=v(r l1 )=v ss relative linearity (2) ?.3 +0.3 mi (3) temperature coefficient of resistance (5) 300 ppm/ c ratiometric temperature (5) coefficient ?0 +20 ppm/? c h /c l /c w potentiometer capacitance (5) 10/10/25 pf see equivalent circuit i ol leakage on dcp pins 0.1 10 ? voltage at pin from v ss to v cc v cc r total
5 of 21 rev 1.6 7/16/03 www.xicor.com X9455 d.c. operating characteristics (over the recommended operating conditions unless otherwise specified.) endurance and data retention capacitance power-up timing a.c. test conditions symbol parameter limits test conditions min. max. units i cc1 v cc supply current (volatile write/read) 3maf scl = 400khz; sda = open; (for 2-wire, active, read and volatile write states only) i cc2 v cc supply current (active) 3maf scl = 200khz; (for u/d interface, increment, decrement) i cc3 v cc supply current (nonvolatile write) 5maf scl = 400khz; sda = open; (for 2-wire, active, nonvolatile write state only) i sb v cc current (standby) 20 ? v cc = +5.5v; v in = v ss or v cc ; sda = v cc ; (for 2-wire, standby state only) i l leakage current, bus interface pins -10 10 ? voltage at pin from v ss to v cc v ih input high voltage v cc x 0.7 v cc + 1 v v il input low voltage ? v cc x 0.3 v v ol sda pin output low voltage 0.4 v i ol = 3ma parameter min. units minimum endurance 100,000 data changes per bit data retention 100 years symbol test max. units test conditions c in/out (5) input / output capacitance (sda) 8 pf v out = 0v c in (5) input capacitance (ds0, ds1, cs , u/d , scl, wp , a2, a1 and a0 ) 6pfv in = 0v symbol parameter max. units t d (5)(9) power up delay from v cc power up (v cc above 2.7v) to wiper position recall com- pleted, and communication interfaces ready for operation. 2ms i nput pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing threshold level v cc x 0.5 external load at pin sda 2.3k ? to v cc and 100 pf to v ss
6 of 21 rev 1.6 7/16/03 www.xicor.com X9455 2-wire interface timing(s) sda vs. scl timing wp , a0, a1, and a2 pin timing symbol parameter min. max. units f scl clock frequency 400 khz t high clock high time 600 ns t low clock low time 1300 ns t su:sta start condition setup time 600 ns t hd:sta start condition hold time 600 ns t su:sto stop condition setup time 600 ns t su:dat sda data input setup time 100 ns t hd:dat sda data input hold time 30 ns t r (5) scl and sda rise time 300 ns t f (5) scl and sda fall time 300 ns t aa (5) scl low to sda data output valid time 0.9 ? t dh sda data output hold time 0 ns t in (5) pulse width suppression time at scl and sda inputs 50 ns t buf (5) bus free time (prior to any transmission) 1200 ns t su:wpa (5) a0, a1, a2 and wp setup time 600 ns t hd:wpa (5) a0, a1, a2 and wp hold time 600 ns t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda (input timing) sda (output timing) t f t low t buf t aa t r t hd:wp scl sda in wp , a0, a1, or a2 t su:wp clk 1 start stop
7 of 21 rev 1.6 7/16/03 www.xicor.com X9455 increment/decrement timing increment/decrement timing symbol parameter limits units min. typ. (4) max. t ci cs to scl setup 600 ns t id (5) scl high to u/d , ds0 or ds1 change 600 ns t di (5) u/d , ds0 or ds1 to scl setup 600 ns t il scl low period 2.5 ? t ih scl high period 2.5 ? t ic scl inactive to cs inactive (nonvolatile store setup time) 1s t cphs cs deselect time (store) 10 ms t cphns (5) cs deselect time (no store) 1 s t iw (5) scl to r w change 100 500 ? t cyc scl cycle time 5 s t r , t f (5) scl input rise and fall time 500 ? cs scl u/d r w t ci t il t ih t cyc t id t di t iw mi (3) t ic t cphs t f t r 10% 90% 90% t cphns ds0, ds1
8 of 21 rev 1.6 7/16/03 www.xicor.com X9455 high-voltage write cycle timing xdcp timing notes: (1) absolute linearity is utilized to determine actual wiper voltage versus expected voltage = [v(r w(n)(actual) )?(r w(n)(expected) )]/mi v(r w(n)(expected) ) = n(v(r h )-v(r l ))/255 + v(r l ), with n from 0 to 255. (2) relative linearity is a measure of the error in step size between taps = [v(r w(n+1) )?v(r w(n) ) + mi)]/mi , with n from 0 to 254 (3) 1 ml = minimum increment = [v(r h )?(r l )]/255. (4) typical values are for t a = 25? and nominal supply voltage. (5) this parameter is not 100% tested. (6) ratiometric temperature coef?ient = (v(r w ) t1(n) ?(r w ) t2(n) )/[v(r w ) t1(n) (t1?2)] x 10 6 , with t1 & t2 being 2 temperatures, and n from 0 to 255. (7) measured with wiper at tap position 255, r l grounded, using test circuit. (8) t wc is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. it is the t ime from a valid stop condition at the end of a write sequence of a 2-wire interface write operation, or from the rising edge of cs of a valid ?tore operation of the up/down interface, to the end of the self-timed internal nonvolatile write cycle. (9) the recommended power up sequence is to apply v cc /v ss ?st, then the potentiometer voltages. during power up, the data sheet parameters for the dcp do not fully apply until t d after v cc reaches its ?al value. in order to prevent unwanted tap position changes, or an inadvertant store, bring the cs pin high before or concurrently with the v cc pin on power up. symbol parameter typ. max. units t wc (8)(5) non-volatile write cycle time 5 10 ms symbol parameter min. max. units t wrl (5) scl rising edge to wiper code changed, wiper response time after instruction issued (all load instructions) 520s test circuit equivalent circuit force current test point r w c h c l r w r total c w r h r l
9 of 21 rev 1.6 7/16/03 www.xicor.com X9455 pin descriptions bus interface pins s erial d ata i nput /o utput (sda) the sda is a bidirectional serial data input/output pin for the 2-wire interface. it receives device address, operation code, wiper register address and data from a 2-wire external master device at the rising edge of the serial clock scl, and it shifts out data after each falling edge of the serial clock scl. sda requires an external pull-up resistor, since its an open drain output. s erial c lock (scl) this input is the serial clock of the 2-wire and up/down interface. d evice a ddress (a2?0) the address inputs are used to set the least signi?ant 3 bits of the 8-bit 2-wire interface slave address. a match in the slave address serial data stream must be made with the address input pins in order to initiate communication with the X9455. a maximum of 8 devices may occupy the 2-wire serial bus. c hip s elect (cs ) when the cs pin is low, increment or decrement operations are possible using the scl and u/d pins. the 2-wire interface is disabled at this time. when cs is high, the 2-wire interface is enabled. u p or d own c ontrol (u/d ) the u/d input pin is held high during increment oper- ations and held low during decrement operations. dcp s elect (ds1-ds0) the ds1-ds0 select one of the four dcps for an up/ down interface operation. h ardware w rite p rotect i nput (wp ) when the wp pin is set low, ?rite operations to non volatile dcp data registers are disabled. this includes both 2-wire interface non-volatile ?rite? and up/down interface ?tore operations. dcp pins r h0 , r l0 , r h1 , r l1 these pins are equivalent to the terminal connections on mechanical potentiometers. since there are two dcps, there is one set of r h and r l for each dcp. r w0a , r w0b , r w1a , and r w1b the wiper pins are equivalent to the wiper terminals of mechanical potentiometers. since there are two wipers per dcp, there are four r w pins.
X9455 10 of 21 rev 1.6 7/16/03 www.xicor.com principles of operation the X9455 is an integrated circuit incorporating two resistor arrays with dual wipers on each array, their associated registers and counters, and the serial inter- face logic providing direct communication between the host and the digitally controlled potentiometers. this section provides detail description of the following: resistor array up/down interface 2-wire interface resistor array description the X9455 is comprised of two resistor arrays. each array contains 255 discrete resistive segments that are connected in series. the physical ends of each array are equivalent to the ?ed terminals of a mechanical potentiometer (r hi and r li inputs). (see figure 1.) each array has two independent wipers. at both ends of each array and between each resistor segment are two switches, one connected to each of the wiper pins (r wia and r wib ). within each individual array only one switch of each wiper may be turned on at a time. these switches are controlled by two wiper counter register (wcr). the 8-bits of the wcr are decoded to select and enable one of 256 switches. note that each wiper has a dedicated wcr. when all bits of a wcr are zeroes, the switch closest to the corresponding r l pin is selected. when all bits of a wcr are ones, the switch closest to the corresponding r h pin is selected. the wcrs are volatile and may be written directly. there are four non-volatile data registers(dr) associ- ated with each wcr. each dr can be loaded into wcr. all drs and wcrs can be read or written. power up and down requirements during power up cs must be high to avoid inadvertant ?tore operations. at power up, the contents of data registers level 0 (dr0a0, dr0b0, dr1a0, and dr1b0), are loaded into the corresponding wiper counter register. figure 1. detailed block diagram of one dcp one of wcria[7:0] r hi r wia r li = ff hex 255 254 255 256 decoder volatile 8-bit wiper counter register wcria four non-volatile data registers dria0, dria1, dria2, and dria3 ??is either 0 or 1 wcrib[7:0] = 00 hex 1 0 r wib 254 0 1 wcrib[7:0] = ff hex wcria[7:0] = 00 hex volatile 8-bit wiper counter register wcrib four non-volatile data registers drib0, drib1, drib2, and drib3 2-wire and up/down interfaces . . . . . .
11 of 21 rev 1.6 7/16/03 www.xicor.com X9455 up/down interface operation the scl, u/d , cs , ds0 and ds1 inputs control the movement of the wiper along the resistor array. with cs set low the device is selected and enabled to respond to the u/d and scl inputs. high to low transitions on scl will increment or decrement (depending on the state of the u/d input) a wiper counter register selected by ds0 and ds1. the output of this counter is decoded to select one of 256 wiper positions along the resistor array. the value of the counter is stored in nonvolatile data register level 0 of the corresponding wcr whenever cs transitions high while the scl and wp inputs are high (see table 1). during a ?tore operation bits wcrsel1 and wcrsel0 in the status register must be both ?? which is their power up default value. other combinations are reserved and must not be used. the system may select the X9455, move a wiper, and deselect the device without having to store the latest wiper position in nonvolatile memory. after the wiper movement is performed as described above and once the new position is reached, the system must keep scl low while taking cs high. the new wiper pos- tion is maintained until changed by the system or until a power-down/up cycle recalled the previously stored data. this procedure allows the system to always power-up to a preset value stored in nonvolatile memory; then during system operation minor adjustments could be made. the adjustments might be based on user prefer- ence, system parameter changes due to temperaure drift, etc. the state of u/d may be changed while cs remains low. this allows the host system to enable the device and then move the wiper up and down until the proper trim is attained. the 2-wire interface is disabled while cs remains low. table 1. dcp selection for up/down control mode selection for up/down control *while in standby, the 2-wire interface is enabled ds1 ds0 selected wiper control register 0 0 wiper a of dcp0 1 1 wiper b of dcp0 1 0 wiper a of dcp1 0 1 wiper b of dcp1 cs scl u/d mode l h wiper up l l wiper down h x store wiper position to non- volatile memory if wp pin is high. no store, return to stand- by, if wp pin is low. h x x standby* l x no store, return to standby l h wiper up (not recommended) l l wiper down (not recommended)
X9455 12 of 21 rev 1.6 7/16/03 www.xicor.com 2-wire serial interface protocol overview the device supports a bidirectional bus oriented protocol. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. the X9455 operates as a slave in all applications. all 2-wire interface operations must begin with a start, followed by a slave address byte. the slave address selects the X9455, and speci?s if a read or write operation is to be performed. all communication over the 2-wire interface is conducted by sending the msb of each byte of data ?st. serial clock and data data states on the sda line can change only while scl is low. sda state changes while scl is high are reserved for indicating start and stop conditions. see figure 2. on power up of the X9455, the sda pin is in the input mode. serial start condition all commands are preceded by the start condition, which is a high to low transition of sda while scl is high. the device continuously monitors the sda and scl lines for the start condition and does not respond to any command until this condition has been met. see figure 2. serial stop condition all communications must be terminated by a stop condition, which is a low to high transition of sda while scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued after the transmitting device has released the bus. see figure 2. figure 2. valid data changes, start, and stop conditions sda scl start data data stop stable change data stable
13 of 21 rev 1.6 7/16/03 www.xicor.com X9455 serial acknowledge an ack (acknowledge), is a software convention used to indicate a successful data transfer. the transmitting device, either master or slave, releases the bus after transmitting eight bits. during the ninth clock cycle, the receiver pulls the sda line low to acknowledge the reception of the eight bits of data. see figure 3. the device responds with an ack after recognition of a start condition followed by a valid slave address byte. a valid slave address byte must contain the device type identi?r 0101, and the device address bits matching the logic state of pins a2, a1, and a0. see figure 4. if a write operation is selected, the device responds with an ack after the receipt of each subsequent eight-bit word. in the read mode, the device transmits eight bits of data, releases the sda line, and then monitors the line for an ack. the device continues transmitting data if an ack is detected. the device terminates further data transmissions if an ack is not detected. the master must then issue a stop condition to place the device into a known state. figure 3. acknowledge response from receiver sda output from transmitter sda output from receiver 8 1 9 start ack scl from master
X9455 14 of 21 rev 1.6 7/16/03 www.xicor.com slave address byte following a start condition, the master must output a slave address byte (refer to ?ure 4.). this byte includes three parts: the four msbs (sa7-sa4) are the device type identi?r, which must always be set to 0101 in order to select the X9455. the next three bits (sa3-sa1) are the device address bits (as2-as0). to access any part of the X9455s memory, the value of bits as2, as1, and as0 must correspond to the logic levels at pins a2, a1, and a0 respectively. the lsb (sa0) is the r/w bit. this bit de?es the operation to be performed on the device being addressed. when the r/w bit is ?? then a read operation is selected. a ? selects a write operation . figure 4. slave address (sa) format nonvolatile write acknowledge polling after a nonvolatile write command sequence is correctly issued (including the ?al stop condition), the X9455 initiates an internal high voltage write cycle. this cycle typically requires 5 ms. during this time, any read or write command is ignored by the X9455. write acknowledge polling is used to determine whether a high voltage write cycle is completed. during acknowledge polling, the master ?st issues a start condition followed by a slave address byte. the slave address byte contains the X9455s device type identi?r and device address. the lsb of the slave address (r/w ) can be set to either 1 or 0 in this case. if the device is busy within the high voltage cycle, then no ack is returned. if the high voltage cycle is completed, an ack is returned and the master can then proceed with a new read or write operation. (refer to ?ure 5.) figure 5. acknowledge polling sequence 2-wire serial interface operation X9455 digital potentiometer register organization refer to the functional diagram on page 1. there are 2 digital potentiometers, referred to as dcp0, and dcp1. each potentiometer has two volatile wiper control registers (wcrs). each wiper has four non- volatile registers to store wiper position or general data. see table 2 for register numbering. sa6 sa7 sa5 sa3 sa2 sa1 sa0 device type identifier read or sa4 slave address bit(s) description sa7?a4 device type identifier sa3?a1 device address sa0 read or write operation select r/w 0101 address device as0 as1 as2 write ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes no continue normal read or write command sequence proceed yes complete. continue command sequence. high voltage issue stop
15 of 21 rev 1.6 7/16/03 www.xicor.com X9455 table 2. register numbering the registers are organized in pages of four, with one page consisting of the four volatile wcrs, a second page consisting of the level 0 data registers, and so forth. these pages can be written four bytes at at time. in this manner all four potentiometer wcrs can be updated in a single serial write (see page write opera- tion), as well as all four registers of a given page in the dr array. the unique feature of the X9455 device is that writing or reading to a data register of a given wiper automat- ically updates the wcr of that wiper with the new value. in this manner data can be moved from a partic- ular wiper register to that wipers wcr just by perform- ing a 2-wire read operation. simultaneously, that data byte can be utilized by the host. status register organization the status register (sr) is used in read and write operations to select the appropriate wiper register. before any wiper register can be accessed, the sr must be set to the correct value. it is accessed by setting the address byte to 07h (write to slave address, then to address 07h). the sr is volatile and defaults to 00h on power up. it is an 8-bit register containing three control bits in the 3 lsbs as follows: bits wcrsel0 and wcrsel1 determine which data register of a wiper is selected in a given operation. nvenable is used to select the volatile wcr if ?? and one of the non volatile wiper registers if ?? table 3 shows this register organization. table 3. status register contents for wcr and dr selection for 2-wire interface note: x means either 0 or 1, nn = 0a, 0b, 1a, or 1b wiper addressing for 2-wire interface once the data register level has been selected by a 2-wire instruction, then the wiper is determined by the address byte of the following instruction. note again that this enables a complete page write of all four potentiometers at once a particular wiper register has been chosen. the register addresses accessible in the X9455 include: table 4. addressing for 2-wire interface address byte all other address bits in the address byte must be set to ? during 2-wire write operations and their value should be ignored when read. dcp0 dcp1 wiper reg. wcr0a wcr0b wcr1a wcr1b level 0 dr0a0 dr0b0 dr1a0 dr1b0 level 1 dr0a1 dr0b1 dr1a1 dr1b1 level 2 dr0a2 dr0b2 dr1a2 dr1b2 level 3 dr0a3 dr0b3 dr1a3 dr1b3 76543 2 1 0 reserved wcrsel1 wcrsel0 nvenable register selected wcrsel1 wcrsel0 nvenable wcrnn x x 0 drnn0 0 0 1 drnn1 0 1 1 drnn2 1 0 1 drnn3 1 1 1 address (hex) contents 0 wiper 0a 1 wiper 1b 2 wiper 1a 3 wiper 0b 4 not used 5 not used 6 not used 7 status register
16 of 21 rev 1.6 7/16/03 www.xicor.com X9455 byte write operation for any byte write operation, the X9455 requires the slave address byte, an address byte, and a data byte (see figure 6). after each of them, the X9455 responds with an ack. the master then terminates the transfer by generating a stop condition. at this time, if the write operation is to a volatile register (wcr, or sr), the X9455 is ready for the next read or write operation. if the write operation is to a nonvolatile register (dr), and the wp pin is high, the X9455 begins the internal write cycle to the nonvolatile memory. during the internal nonvolatile write cycle, the X9455 does not respond to any requests from the master. the sda output is at high impedance. the sr bits and wp pin determine the register being accessed through the 2-wire interface. see table 1 on page 11. as noted before, any write operation to a data register (dr), also writes to the corresponding wcr. for example, to write 3ahex to the level 1 data regis- ter of wiper 1a (dr1a1) the following sequence is required: during the sequence of this example, wp pin must be high, and a0, a1, and a2 pins must be low. when com- pleted, the dr1a1 register of wiper 1a will be set to 3ah, and also the wcr1a. figure 6. byte write sequence start slave address 0101 0000 ack address byte 0000 0111 ack data byte 0000 0011 ack stop start slave address 0101 0000 ack address byte 0000 0010 ack data byte 0011 1010 ack stop (hardware address = 000, and a write command) (indicates status register address) (data register level 1 and nvenable selected) (hardware address = 000, (access wiper 1a) (write data byte 3ah) write command) s t a r t s t o p slave address address byte data byte a c k signals from the master signals from the slave a c k 0 0 0 11 a c k write signal at sda
17 of 21 rev 1.6 7/16/03 www.xicor.com X9455 page write operation as stated previously, the memory is organized as a single status register (sr), and four pages of four registers each. each page contains one data register for each wiper. normally a page write operation will be used to ef?iently update all four data registers and wcr in a single write command. note the special sequence for writing to a page: first wiper 0a, then 1b, then 1a, then 0b as shown in ?ure 7. figure 7. page write sequence* *page writes may wrap around to the ?st address on a page from the last address. in order to perform a page write operation to the mem- ory array, the nvenable bit in the sr must ?st be set to ?? a page write operation is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the ?st data byte is transferred, the master can transmit up to 4 bytes (see figure 8). after the receipt of each byte, the X9455 responds with an ack, and the internal wcr address is incremented by one. the page address remains constant. when the address reaches the end of the page, it ?olls over and goes back to the ?st byte of the same page. for example, if the master writes three bytes to a page starting at location dr1a2, the ?st two bytes are written to locations dr1a2 and dr0b2, while the last byte is written to location dr0a2. afterwards, the wcr address would point to location dr1b2. if the master supplies more than four bytes of data, then new data overwrites the previous data, one byte at a time. the master terminates the loading of data bytes by issuing a stop condition, which initiates the nonvolatile write cycle. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. if the wp pin is high, the nonvolatile write cycle doesn? start and the bytes are discarded. notice that the data bytes are also written to the wcr of the corresponding wcrs, therefore in the above example, wcr1a, wcr0b, and wcr0a are also written. figure 8. page write operation wcr wcr0a wcr1b wcr1a wcr0b dr level 0 dr0a0 dr1b0 dr1a0 dr0b0 dr level 1 dr0a1 dr1b1 dr1a1 dr0b1 dr level 2 dr0a2 dr1b2 dr1a2 dr0b2 dr level 3 dr0a3 dr1b3 dr1a3 dr0b3 2 < n < 4 signals from the master signals from the slave signal at sda s t a r t slave address address byte a c k a c k 0 0 0 11 data byte (1) s t o p a c k a c k data byte (n) write
X9455 18 of 21 rev 1.6 7/16/03 www.xicor.com move/read operation the move/read operation simultaneously reads the contents of a data register and moves the contents into the corresponding dcps wcr. if more than one data register byte is read, then all wipers accessed will have their wcrs updated with the data register values that were read. move/read operation consists of a one byte, or three byte instruction followed by one or more data bytes (see figure 9). to read an arbitrary byte, the master initiates the operation issuing the following sequence: a start, the slave address byte with the r/w bit set to ?? an address byte, a second start, and a second slave address byte with the r/w bit set to ?? after each of the three bytes, the X9455 responds with an ack. then the X9455 transmits data bytes as long as the master responds with an ack during the scl cycle following the eighth bit of each byte. the master terminates the move/read operation (issuing a stop condition) following the last bit of the last data byte. the ?st byte being read is determined by the current wiper address and by the status register bits, according to table 1 on page 11. if more than one byte is read, the wcr address is incremented by one after each byte, in the same way as during a page write operation. after reaching wcr0b, the wcr address ?olls over to wcr0a. on power up, the address pointer is set to the data register 0 of wcr0a. figure 9. move/read sequence signals from the master signals from the slave signal at sda s t a r t slave address with r/w =0 address byte a c k a c k 0 0 0 11 s t o p a c k 0 1 0 11 slave address with r/w =1 a c k s t a r t last read data byte first read data byte a c k one or more data bytes current address read setting the current address random address read
19 of 21 rev 1.6 7/16/03 www.xicor.com X9455 applications information basic configurations of electronic potentiometers application circuits v r rw0 four terminal potentiometer; variable voltage divider four-wiper dcp rw1 rw0a rw0b rw1a rw1b pot0 pot1 rh rl poti window comparator shunt limiter function generator + v s v o v+ + v ul v ll v+ + v s v o } } v r + } mr nr pr + v o } } } mr nr pr c +
20 of 21 rev 1.6 7/16/03 www.xicor.com X9455 programmable state variable filter + v o (bp) } } } mr1 nr1 pr1 c v s + v o (lp) } } } mr2 nr2 pr2 c + r3 v o (hp) programmable ladder networks } } } mr nr pr r1 c1 a2 a1 a3 + v o } c2 r 4 c1 } r 3 } r 2 } r 1 r w3 r w2 r w1 wien bridge oscillator + + r 3 r 4 r 5 two wiper dcp z 1 z 2 z in = z 1 z 2 r 3 * r 5 r 4 ( ) * generalized impedance converter
characteristics subject to change without notice. 21 of 21 limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. trademark disclaimer: xicor and the xicor logo are registered trademarks of xicor, inc. autostore, direct write, block lock, serialflash, mps, biaslo ck and xdcp are also trademarks of xicor, inc. all others belong to their respective owners. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicors products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. ?icor, inc. 2003 patents pending rev 1.6 7/16/03 www.xicor.com X9455 packaging information note: all dimensions in inches (in parentheses in millimeters) 24-lead plastic, tssop, package code v24 .169 (4.3) .177 (4.5) .252 (6.4) bsc .026 (.65) bsc .303 (7.70) .311 (7.90) .002 (.06) .005 (.15) .047 (1.20) .0075 (.19) .0118 (.30) see detail ? .031 (.80) .041 (1.05) .010 (.25) .020 (.50) .030 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical 08

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